1. Field of the Invention
The present invention relates to a method for manufacturing a single crystal semiconductor layer. In specific, the present invention relates to a method for manufacturing a single crystal semiconductor layer over a substrate with an insulating layer interposed therebetween, that is, relates to a method for manufacturing an SOI (silicon on insulator) substrate.
2. Description of the Related Art
In recent years, an integrated circuit using an SOI (silicon on insulator) substrate in which a thin single crystal semiconductor layer is formed on an insulating surface, instead of a bulk silicon wafer, has been researched. An SOI substrate enables parasitic capacitance generated by a drain of a transistor and a semiconductor substrate to be small. Therefore, an SOI substrate has greatly attracted attention for its ability to improve performance of a semiconductor integrated circuit.
The Smart Cut (registered trademark) method is known as one of methods for manufacturing an SOI substrate (for example, see Patent Document 1). An outline of a method for manufacturing an SOI substrate by the Smart Cut (registered trademark) method is described below. First, hydrogen ions are implanted into a silicon wafer by an ion implantation method for forming a microbubble layer at a predetermined depth from the surface. Then, the silicon wafer into which the hydrogen ions are implanted is bonded to another silicon wafer with a silicon oxide film interposed therebetween. After that, heat treatment is performed so that a part of the silicon wafer into which the hydrogen ions are implanted is separated in a thin film shape at the microbubble layer. Accordingly, a single crystal silicon layer is provided over the other bonded silicon wafer. The Smart Cut (registered trademark) method may be referred to as a hydrogen ion implantation separation method.
As another method for manufacturing an SOI substrate, a method called ELTRAN is known (for example, see Patent Document 2). According to ELTRAN, a single crystal silicon layer is provided over a silicon wafer as follows: a silicon wafer is anodized so as to form a porous silicon layer; a single crystal silicon layer is formed on the porous silicon layer by an epitaxial growth method; a thermal oxidation film is formed over the single crystal silicon layer; the silicon wafer is bonded to another silicon wafer; and the single crystal silicon layer is separated at the porous silicon layer by etching or water jetting or the like.
Note that in these methods, CMP treatment or heat treatment at high temperature (about lower than or equal to 1200° C.) needs to be performed after a single crystal silicon layer is formed so that the planarity of the surface of the single crystal silicon layer is improved and a defect in the single crystal silicon layer is repaired.
[Citation List]
    [Patent Document 1] Japanese Published Patent Application No. H05-211128    [Patent Document 2] Japanese Published Patent Application No. H05-217821